1. 华南理工大学 发光材料与器件国家重点实验室,广东 广州,510640
2. 华南理工大学 电子与信息学院, 广东 广州 510640
3. 广州新视界光电科技有限公司,广东 广州,510730
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LIN Yi-zhen, HU Yu-feng, ZHOU Lei, et al. New Low-power Gate Driver Circuit Integrated by Metal Oxide Thin Film Transistors. [J]. Chinese Journal of Luminescence 41(1):103-109(2020)
LIN Yi-zhen, HU Yu-feng, ZHOU Lei, et al. New Low-power Gate Driver Circuit Integrated by Metal Oxide Thin Film Transistors. [J]. Chinese Journal of Luminescence 41(1):103-109(2020) DOI: 10.3788/fgxb20204101.0103.
金属氧化物薄膜晶体管(TFT)属于耗尽型器件,其集成的TFT的行驱动电路一般采用双负电源方案,存在与外围驱动芯片的匹配困难和功耗较大的不足。本文设计了一种新型耦合电路结构,可以产生比负电源更低的电压从而完全关闭输出模块的下拉晶体管,防止氧化物TFT耗尽模式引起的电流泄露问题,并由此设计了新型氧化物TFT行驱动电路拓扑。由于只采用一个负电源,其电源电压范围比采用双负电源方案的小,从而节省了功耗且有利于与外围驱动芯片的匹配连接。实验结果表明,基于刻蚀阻挡层(ESL)结构的氧化物TFT工艺,在玻璃衬底上成功制备了该行驱动电路,在电阻负载,R,L,=3 k和容性负载,C,L,=30 pF下,所设计的行驱动电路在33.3 kHz时钟频率下实现脉宽10 s的全摆幅输出,每级功耗仅为160 W。基于新型耦合电路结构的行驱动电路能够满足60 Hz的刷新频率的1 9801 080分辨率的显示需求。
The gate driver circuit integrated by metal oxide thin film transistors(TFTs) generally adopts a double negative power supply scheme due to their depletion mode, which has difficulty in matching with the peripheral driving chip and a large power consumption. In the proposed circuit, a new coupling circuit structure is designed in order to generate a lower voltage than the negative voltage applied in the circuit. Consequently, the pull-down transistors of the output module can be completely turned off to prevent the current leakage problem caused by the depletion mode of oxide TFT. Thus, the power consumption can be saved since the voltage range of power source for single negative voltage source method is smaller than that for the two negative voltage sources method. In addition, the gate driver circuit using a single negative voltage source is easy to comply with the peripheral driving ICs. The proposed gate driver circuit has been fabricated on glass by metal oxide TFTs with the etch-stop layer (ESL) structure. The experimental results show that the proposed gate driver circuit achieves a full swing output with a pulse width of 10 s at the clock frequency of 33.3 kHz under the load of ,R,L,=3 k and,C,L,=30 pF. The power consumption of the gate driver circuit is measured as 160 W. The proposed gate driver circuit is suitable for a 1 9801 080 resolution display at a frame rate of 60 Hz.
In-Zn-O薄膜晶体管行驱动电路新型耦合电路结构
In-Zn-O thin film transistorsgate drivernew coupling circuit structure
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