Thermal Impact of High Power Semiconductor Laser with Voids in Solder Layer

ZHANG Xiao-lei; BO Bao-xue; ZHANG Zhe-ming; GU Hua-xin; LIU Li-ning; XU Yu-meng; QIAO Zhon

doi:10.3788/fgxb20183907.0983

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Thermal Impact of High Power Semiconductor Laser with Voids in Solder Layer

更新时间：2020-08-12

- Thermal Impact of High Power Semiconductor Laser with Voids in Solder Layer
- Chinese Journal of Luminescence Vol. 39, Issue 7, Pages: 983-990(2018)
- 作者机构：
  
  长春理工大学高功率半导体激光国家重点实验室,吉林长春,130022
- 作者简介：
- 基金信息：
  
  Supported by State's Key Project of Research and Development Plan(SQ2017YFGX020046)(
- DOI：10.3788/fgxb20183907.0983
  CLC： TN248.4
- Received：01 November 2017，
  
  Revised：02 March 2018，
  
  Published Online：23 March 2018，
  
  Published：05 July 2018
- 稿件说明：
移动端阅览
张晓磊, 薄报学, 张哲铭等. 烧结空洞对半导体激光器热分布的影响[J]. 发光学报, 2018,39(7): 983-990

ZHANG Xiao-lei, BO Bao-xue, ZHANG Zhe-ming etc. Thermal Impact of High Power Semiconductor Laser with Voids in Solder Layer[J]. Chinese Journal of Luminescence, 2018,39(7): 983-990
张晓磊, 薄报学, 张哲铭等. 烧结空洞对半导体激光器热分布的影响[J]. 发光学报, 2018,39(7): 983-990 DOI： 10.3788/fgxb20183907.0983.

ZHANG Xiao-lei, BO Bao-xue, ZHANG Zhe-ming etc. Thermal Impact of High Power Semiconductor Laser with Voids in Solder Layer[J]. Chinese Journal of Luminescence, 2018,39(7): 983-990 DOI： 10.3788/fgxb20183907.0983.

摘要

在半导体激光器芯片与热沉的焊接过程中不可避免地会在焊料层产生一些空洞，而空洞会在铟的电迁移以及电热迁移作用下慢慢变大，使芯片局部温度迅速上升，进而影响半导体激光器的性能。针对10 W的808 nm单管焊装半导体激光器建立三维有限元模型，分别模拟计算了空洞面积、空洞厚度和空洞位置与结温的关系。芯片出光面边缘的有源区区域形成的空洞对芯片的结温影响更为显著，最后得到空洞面积与器件结温的关系，并表明对空洞率控制的重要性。

Abstract

Semiconductor laser chip and heat sink in the welding process will inevitably produce some holes in the solder layer. These voids will become larger in the electromigration and electromigration of indium. The local temperature of the chip rises rapidly

and affects the performance of semiconductor lasers. A three-dimensional finite element model of 808 nm single-tube welding semiconductor lasers with power of 10 W was established

and the relationship between void area

void thickness and void position was calculated. The results show that the voids formed in the active region of the edge of the chip have a more significant influence on the junction temperature of the chip. Finally

the relationship between cavity area and junction temperature was obtained. The importance of void ratio control was also demonstrated.

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Keywords

references

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