The flat panel display(FPD) such as FED and PDP have been developed rapidly in recent years.The FPD needs high-voltage driven signal

so the driven circuit must include high-voltage interface.As the development of CMOS technology

high-voltage CMOS devices and low-voltage circuits can be integrated in the same chip

so the cost of the system can be reduced and the reliability of the circuit can be improved.The LDMOS structure was taken as the structure of the high-voltage devices is LDMOS because the fabrication of LDMOS can be compatible with standard CMOS process.Combined with 0.8 μm CMOS technique of IMECAS(Institute of Microelectronics

Chinese Academy of Sciences)

the process to fabricate high-voltage CMOS devices is designed by Synopsys TCAD software(Tsuprem-4 and MEDICI).In order to guarantee the validity of simulation results

key technology parameters should be calibrated based on the experimental results.According to the calibrated parameters

the drift region of LDMOS was optimized based on the RESURF technique and the whole process was simulated by TCAD software.The simulated results show that the breakdown voltage of high-voltage NMOS device is 220 V

the threshold voltage and driven ability of HVNMOS are 0.8 Vand 1×10

-4

A/μm

respectively;the breakdown voltage of highvoltage PMOS device is -135 V

the threshold voltage and driven ability of HVPMOS are -9.7 V and 1.8×10

-4

A/μm

respectively.The high-voltage CMOSdevices can be used in high-voltage integrated circuit(HV-IC) such as driver ICs for PDPand FED.